1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory such as a mask ROM.
2. Description of the Background Art
A mask ROM disclosed in Japanese Patent Laying-Open No. 5-275656 (1993) is generally known as an exemplary memory.
FIG. 8 is a plane layout diagram showing the structure of a conventional contact-mask ROM. Referring to FIG. 8, a plurality of word lines 101 and a plurality of bit lines 102 are arranged to intersect with each other in the conventional contact-mask ROM. Memory cells 104 formed by single transistors 103 respectively are arranged on positions corresponding to the intersections between the plurality of word lines 101 and the plurality of bit lines 102 respectively. The word lines 101 are formed on a substrate (not shown) through gate insulating films (not shown) of the transistors 103. These word lines 101 function also as gate electrodes of the transistors 103. On a surface portion of the substrate (not shown) located on the region formed with each memory cell 104, a pair of impurity regions 105 and 106 serving as source/drain regions of the corresponding transistor 103 are formed to hold a region located under the corresponding word line 101 therebetween.
Source lines (GND lines) 107 are provided on the impurity regions 105 functioning either the source regions or the drain regions of the transistors 103, to extend along the extensional direction of the word lines 101. The source lines 107 and the impurity regions 105 are connected with each other through plugs 108. Thus, the impurity regions 105 are supplied with the ground potential (GND). The conventional mask ROM sets data of each memory cell 104 including the transistor 103 to “0” or “1” depending on whether or not the impurity region 106 functioning as either the drain region or the source region of the transistor 103 is connected to the corresponding bit line 102.
In the conventional mask ROM shown in FIG. 8, however, the memory cell size is disadvantageously increased due to the transistors 103 provided in correspondence to the respective memory cells 104.